1. Field of the Invention
This invention relates to the construction of integrated circuit structures. More particularly, this invention relates to the respective construction of vias, and trenches for metal lines in multiple dielectric layers useful for the formation of filled vias and metal interconnects comprising a portion of an integrated circuit structure.
2. Description of the Related Art
Conventionally, in the construction of a metal wiring or interconnect structure for an integrated circuit structure, a metal layer is blanket deposited over a dielectric layer containing filled (or unfilled) vias and this metal layer is then patterned, using an appropriate mask, into the desired metal interconnect structure. Unfortunately, not all metals are easily patterned (etched) in this manner.
To form a metal interconnect structure using such metals which are not easily etched, it has been proposed to form a series of trenches in an upper dielectric layer formed over the dielectric layer containing the vias, with the trenches in the upper dielectric layer in registry with the underlying vias. After the trenches are formed, a metal layer is blanket deposited over the entire structure to fill the trenches. Metal deposited on the surface of the dielectric layer containing the trenches is then removed, e.g., by a chemical/mechanical polishing (CMP) process, leaving the desired pattern of metal interconnects in the trenches. In some instances, the same metal deposition step is also used to fill vias, previously formed in another dielectric layer lying below the dielectric layer used for the trench formation.
Several conventional prior art processes have been used to form this type of structure with openings in multiple dielectric layers of an integrated circuit structure wherein one or more vias are formed in a lower dielectric layer, and one or more trenches are then formed, in registry with the vias, in an upper dielectric layer. One such prior art process is illustrated in prior art FIGS. 1-3. A first dielectric layer 10, e.g., a silicon oxide layer, is formed over an integrated circuit structure generally denoted at 2 which may comprise an underlying layer of metal interconnects formed over a dielectric layer on a semiconductor substrate, or a dielectric layer with filled contact openings formed over devices in a semiconductor substrate, or over another dual layer via and trench construct. First dielectric layer 10 may range in thickness from greater than 0.5 micrometers (.mu.m) up to about 2 .mu.m, but typically will be about 1 .mu.m in thickness.
Over first dielectric layer 10 is formed a thin second dielectric layer 20 formed of a different dielectric material than layer 10, e.g., silicon nitride, to permit second dielectric layer 20 to function as an etch stop and an etch mask as will be explained below. Thin second dielectric layer 20 may vary in thickness from about 200 Angstroms (.ANG.) up to about 800 .ANG., and typically will be about 400 .ANG. in thickness.
In this process, a first resist mask layer 30 is then formed over second dielectric layer 20 with one or more openings formed therein, as illustrated at 32, corresponding to the size of one or more vias to be eventually formed in first dielectric layer 10. As shown in FIG. 1, second dielectric layer 20 is etched through opening 32 in first resist mask 30 to form an opening 22 in second dielectric layer 20 which will eventually be used as an etch mask for the formation of a via in first dielectric layer 10. Typically an etch system is used which will be selective to first dielectric layer 10, i.e., will preferentially etch second dielectric layer 20 rather than first dielectric layer 10. For example, when first dielectric layer 10 comprises silicon oxide and second dielectric layer 20 comprises silicon nitride, a CHF.sub.3, CF.sub.4, and O.sub.2 plasma etch system can be used to preferentially etch silicon nitride second dielectric layer 20.
As shown in FIG. 2, after formation of opening 22 in second dielectric layer 20, first resist mask 30 is removed and a third dielectric layer 40 is deposited over second dielectric layer 20. Third dielectric layer 40 comprises a material different than second dielectric layer 20 and may comprise the same material, e.g., silicon oxide, as first dielectric layer 10. Third dielectric layer 40 may be formed in the same thickness range as first dielectric layer 10. As also shown in FIG. 2, a second resist mask 50 is then formed over third dielectric layer 40. Second resist mask 50 has one or more openings therein, as illustrated at 52, corresponding to the size and configuration of a pattern of trenches to be formed in third dielectric layer 40. It will be noted that trench opening 52 in second resist mask 50 is in registry with mask opening 22 in second dielectric layer 20, so that the trench eventually formed in third dielectric layer 40, through mask opening 52, will be in registry with the via formed in first dielectric layer 10 through mask opening 22 in second dielectric layer 20.
After formation of second resist mask 50 over third dielectric layer 40, the structure is subject to an etch using an etch system which will etch third dielectric layer 40 (through mask opening 52 in second resist mask 50) and first dielectric layer 10 (through opening 22 in second dielectric layer 20), but which is selective to second dielectric layer 20, i.e., will preferentially etch the dielectric material of dielectric layers 10 and 40. Second dielectric layer 20 then acts as an etch stop to permit a trench 42 to be formed in third dielectric layer 40 (through mask opening 52 in mask 50). At the same time, second dielectric layer 20 acts as an etch mask to permit formation of via 12 in first dielectric layer 10 through previously formed mask opening 22 in second dielectric layer 20. For example, when first dielectric layer 10 and third dielectric layer 40 both comprises silicon oxide and second dielectric layer 20 comprises silicon nitride, a CF.sub.4, C.sub.4 F.sub.8, and argon plasma etch system can be used to preferentially etch silicon oxide first dielectric layer 10 and silicon oxide third dielectric layer 40. Thus, silicon nitride second dielectric layer 20 functions both as an etch stop (while forming trench opening 42 in third dielectric layer 40) and as an etch mask (when etching via 12 in first dielectric layer 10). The resulting structure is shown in prior art FIG. 3. Resist mask 50 can then be removed, and conventional via and trench lining processing, and via and trench metal filling processing, can then be performed.
While the afore-described process does form the desired via 12 in first dielectric layer 10, while also forming trench 42 in third dielectric layer 40, the additional use of second dielectric layer 20 as an etch mask (rather than merely as an etch stop to permit independent etching of first dielectric layer 10 and third dielectric layer 40), puts additional etching stress on second dielectric layer 20.
Another conventional process which is used for respectively forming vias and trenches in two dielectric layers separated by a thin additional dielectric layer acting as an etch stop is shown in prior art FIGS. 4-6. As shown in FIG. 4, first dielectric layer 10 is again formed over underlying integrated circuit structure 2, and thin second dielectric layer 20 is again formed over first dielectric layer 10. In this process, however, third dielectric layer 40 is then formed directly over second dielectric layer 20 prior to any etching steps. First resist mask 30' is then formed over third dielectric layer 40 with one or more mask openings, such as illustrated by mask opening 34 therein corresponding to the desired size of the trenches to be formed in third dielectric layer 40. An opening 44 corresponding to the desired trench is then formed in third dielectric layer 40 through mask opening 34 by the same selective plasma etching as previously described, as also shown in FIG. 4.
First resist mask 30' is then removed and replaced by second resist mask 50' which is formed over third dielectric layer 40 and into newly formed opening 44 in third dielectric layer 40. As seen in FIG. 5, second resist mask 50' has an opening 54 therein corresponding in size to a via opening to be formed in dielectric layers 10 and 20.
Second dielectric layer 20 and first dielectric layer 10 are then etched through opening 54 in second resist mask 50', using appropriate etchants systems as earlier discussed, to form via opening 24 in second dielectric layer 20 and via opening 14 in first dielectric layer 10, as shown in FIG. 6. It should be noted here, however, that the etchant system(s) used for this step of etching through both first dielectric layer 10 and second dielectric layer 20 need not be selective to either of the first and second dielectric layers, since both will be etched. That is, a common etchant system may be used, if desired, which is capable of etching both the first and second dielectric layers. After forming vias 14 and 24 respectively (via 14/24) in dielectric layers 10 and 20, second resist mask 50' may be removed and the previously described conventional via and trench lining processing, and via and trench metal filling processing, can then be performed.
While this second process does not subject second dielectric layer 20 to the stress of usage as an etch mask as in the process of FIGS. 1-3, it does require a more complicated second resist mask 50' which must partially fill trench opening 44 formed in the third dielectric layer 40, while preserving the desired dimensional integrity of the via opening formed in second resist mask 50'.
Yet a third prior art process has been used for respectively forming vias and trenches in two dielectric layers separated by another thin dielectric layer acting as an etch stop, as shown in prior art FIGS. 7-9. In this process, as in the process of FIGS. 4-6, first, second, and third dielectric layers 10, 20, and 40 are first formed respectively over integrated circuit structure 2, and then first resist mask 30" is applied, having a mask opening 36 therein corresponding to the size of the via to be formed in first dielectric layer 10 and second dielectric layer 20, as shown in FIG. 7. All three dielectric layers (10, 20, and 40) are etched through mask opening 36 in first resist mask 30", as shown in FIG. 7 to form openings 16, 26, and 46, respectively through the three dielectric layers. First resist mask 30" is then removed and replaced by second resist mask 50" which is formed over third dielectric layer 40, as shown in FIG. 8. Second resist mask 50" has a mask opening 56 therein corresponding dimensionally to a desired trench to be formed in third dielectric layer 40. Third dielectric layer 40 is then etched through mask opening 56, as shown in FIG. 9, with second dielectric layer 20 functioning as the etch stop to form trench opening 46a in third dielectric layer 40. Similar to the previously described processes, second resist mask 50'" may then be removed and the previously described conventional via and trench lining processing, and via and trench metal filling processing, can then be performed.
While this third conventional prior art process eliminates the etch mask stress on second dielectric layer 20 of the first process shown in FIGS. 1-3, and also eliminates the complicated second resist mask 50' of the process of FIGS. 4.6, it does result in the need to etch and clean a high aspect ratio opening in the first step where the via opening is formed through all three dielectric layers by forming openings 16, 26, and 46 through respective dielectric layers 10, 20, and 40 using resist mask opening 36.
It would, therefore, be desirable to provide a process capable of respectively forming vias and trenches in multiple dielectric layers which may be separated from one another by a thin dielectric layer acting as an etch stop, while avoiding the etch mask stress on the thin dielectric layer of the process of FIGS. 1-3, the complicated resist mask of the process of FIGS. 4-6, and the high aspect ratio opening of the process of FIGS. 7-9.